[LA-SiGMA-TESC] HPC Special Event: Accelerating Production

[Feng Chen]

Dear All,

The Schedule for the Fall 2015 HPC Training is available at http://www.hpc.lsu.edu/training/tutorials.php.

Our next HPC special event will be held on Wednesday, Oct 14 at 9:00 AM in 307 Frey.

Wednesday, Oct. 14, 2015: Accelerating Production
The LSU HPC User Service team will hold a special event entitled Accelerating Production in the Frey 307 classroom, from 9 am to 11 am, Oct 14th, 2015. All interested students, research associates, professors and researchers at LSU are invited to this special event.
The goal of this event is twofold: to raise the computational research community's awareness of the benefit of leveraging Intel Xeon Phi coprocessors in their research and to engender collaboration between research groups and HPC user consultants by working together on porting their codes to coprocessors. For this event, we do not intend to present technical details and teach users how to write and optimize programs. Instead, we would like to have one-to-one discussions with you to work out a plan on how we can help you to accelerate your application, either by identifying a Xeon Phi-enabled application, modifying how applications are built or rewriting part of the code. You do not have to be a programmer to attend. Actually, the only prerequisite is that running programs on a cluster is an integral part of your research and you would like to accelerate it. Another benefit of having a plan to migrate to Xeon Phi is that it will likely increase your chance of getting a compute allocation on the SuperMIC cluster, which is faster than other LSU HPC clusters even without the Xeon Phi accelerators.
More details about this event and the registration link can be found here:
http://www.hpc.lsu.edu/training/accprod.php

Next HPC Training:

Wednesday, Oct. 21, 2015: Xeon Phi programming
Intel Xeon Phi is a coprocessor based on Many Integrated Core Architecture or MIC. Computer codes can be accelerated substantially with Xeon Phi. More importantly, the programming architecture is based on traditional OpenMP and MPI. It is convenient to migrate your current CPU-based OpenMP or MPI codes to Xeon Phi. The recently launched supercomputer SuperMIC at LSU provides hundreds of compute nodes with Xeon Phis. If you want to accelerate your codes on SuperMIC, this is really the training you can not miss. You will learn how to write, compile and run Xeon-phi codes in this two-session training. In the first session, computing features of Xeon phi and its usage in HPC will be introduced. Then we will focus on state-of-the-art Xeon-phi programming, including native mode and offloading. In the second session, we will introduce symmetric processing with both CPU and Xeon phi. Optimizing and debugging codes will be also covered. Finally we will show some examples for running Xeon-phi enabled applications.
Prerequisites: OpenMP and MPI parallel computation, C or Fortran programming (Either one is fine.), all of the above are assumed but not required.

Please visit http://www.hpc.lsu.edu/training/tutorials.php for more details and register using the link provided.
Users who plan on joining remotely will be provided with a WebEx Link in their registration confirmation email. Please see the system requirements at https://grok.lsu.edu/Categories.aspx?parentCategoryId=3381 .

Please distribute to faculty, staff and students that might be interested.

Thanks,

Feng Chen
IT Consultant
High Performance Computing
Louisiana State University
329 Frey Computing Services Center, Baton Rouge, LA  70803
office 225-578-2924
fchen14 at lsu.edu<mailto:fchen14 at lsu.edu>

-------------- next part --------------
An HTML attachment was scrubbed...
URL: https://mail.loni.org/mailman/private/lasigma-gpu/attachments/20151008/40a761de/attachment.html