[LA-SiGMA-TESC] Fwd: Nersc Training Opportunity on Intel Compilers

[Jian Tao]

-------- Forwarded Message --------
Subject: 	Nersc Training Opportunity on Intel Compilers
Date: 	Fri, 8 May 2015 16:49:39 +0000
From: 	ALCF Media <media at alcf.anl.gov>
Reply-To: 	ALCF Media <media at alcf.anl.gov>
To: 	jtao at cct.lsu.edu



Nersc Training Opportunity on Intel Compilers

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    Using the Intel Compiler as a Performance Optimization and
    Characterization Tool

*Wednesday, May 13 from 10am-12pm PDT*


NERSC will host an in-depth training presentation on using the Intel 
compiler as a performance optimization and characterization tool. The 
presentation will be May 13 from 10am to 12pm PDT. The speaker will be 
Rakesh Krishnaiyer of Intel.

*Details:*
For identified hotspots/analysis done using performance profiling tools 
(such as VTune), we will discuss how to use the compiler reports to 
maximize performance and how to guide the compiler optimizer’s code 
transformations.

The talk will include performance best-known-methods and tips, including 
source code changes in order to improve performance. The talk will also 
help the user understand optimizations done by the compiler in order to 
gain performance.

*Location:*
This event will be presented online using WebEx technology and in person 
at NERSC Oakland Scientific Facility.

*Registration:*
There is no registration for the online event. If you wish to attend 
locally in Oakland, please send email to training at nersc.gov 
<http://anl.us6.list-manage.com/track/click?u=7d7e32ea6092c85ad51b75087&id=1c9b18c9b0&e=15253bd6f3>. 
NERSC's facility is located at 415 20th Street, Oakland, CA. The 
building is easily accessible from the BART 19th Street station.

*Remote Connection Information:*
Use your browser to connect to https://nersc-training.webex.com/ 
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Visit the following remote setup page for connection 
information:https://www.nersc.gov/users/training/events/remote-setup/ 
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