[LA-SiGMA] Announcement: *Travel Award Available* 4th Annual LONI Parallel Programming Workshop and Intel Xeon Phi Workshop

[Feng Chen]

Dear All,

The LSU Information Technology Services, LSU Center for Computation & Technology, Louisiana Optical Network Initiative (LONI) are pleased to announce the following two workshops:


*         4th Annual LONI Parallel Programming Workshop from June 1st through June 3rd, 2015.

*         Intel Xeon Phi Workshop on June 4th, 2015.

Sponsors

Special thanks to the following for their generous support of the LONI Programming Workshop.


*         Louisiana Optical Network Initiative (LONI)

*         Louisiana Alliance for Simulation-Guided Materials Applications (LA-SiGMA).

*         Information Technology Services, Louisiana State University

*         Center for Computation & Technology, Louisiana State University

*         Board of Regents, State of Louisiana

REGISTER NOW if you plan on attending the following events:

Note:


o   The two workshops need to be registered *separately*

o   Requesting Travel Award: There are limited travel funds available for attending the workshops. All participants traveling to Baton Rouge for attending the workshops will be considered for travel awards provided, To be considered for a travel award, please upload a one or two paragraph proposal (in pdf/doc format) describing why a travel award is beneficial to your research for attending the workshop at this link<http://www.hpc.lsu.edu/training/workshopreg.php?topic=4%3Csup%3Eth%3C/sup%3E%20Annual%20LONI%20HPC%20Parallel%20Programming%20Workshop&date=June%201%20-%203,%202015&time=8:00%20AM%20-%205:00%20PM&place=BEC,%20ROOM%201700&desc=loniprog2015.inc&deadline=2015-05-22%2012:00:00&startdate=2015-04-01%2008:00:00#travel> (Requesting Travel Award). If you have registered before but want to request travel award, please just upload the travel proposal from that link<http://www.hpc.lsu.edu/training/workshopreg.php?topic=4%3Csup%3Eth%3C/sup%3E%20Annual%20LONI%20HPC%20Parallel%20Programming%20Workshop&date=June%201%20-%203,%202015&time=8:00%20AM%20-%205:00%20PM&place=BEC,%20ROOM%201700&desc=loniprog2015.inc&deadline=2015-05-22%2012:00:00&startdate=2015-04-01%2008:00:00#travel>.

*4th Annual LONI Parallel Programming Workshop
Date: June 1 - 3, 2015
Time: 8:30 AM - 5:00 PM
Venue: BEC, ROOM 1700
Website: http://www.hpc.lsu.edu/training/workshop.php
Registration Fee: None
Registration opens: April 1, 2015
Registration deadline: May 22, 2015

Description:
This workshop will first introduce users to the concepts of Parallel Programming, then cover how those concepts are applied to solving problems frequently encountered in numerical studies such as matrix-matrix multiplication. Various parallel programming techniques including OpenMP and OpenACC will be the introduced. This workshop will be hands-on oriented, so the attendants should have prior programming experience in C/C++ and/or Fortran.

Schedule (Note: This tentative Schedule is subject to change.)

June 1: Parallel Programming Concepts and OpenMP I
June 2: OpenMP II and OpenACC I
June 3: OpenACC II and Parallel Application Execution

*Intel Xeon Phi Workshop
Date: June 4, 2015
Time: 8:30 AM - 5:00 PM
Venue: BEC, ROOM 1700
Website: http://www.hpc.lsu.edu/training/workshop.php
Registration Fee: None
Registration opens: April 8, 2015
Registration deadline: June 1, 2015

Description:
Colfax Developer Training (CDT) is an in-depth intensive course on efficient parallel programming of Intel Xeon family processors and Intel Xeon Phi coprocessors.

The 1-day labs course (CDT 102) features hands-on exercises on the available programming models and best optimization practices for the Intel many-core platform, and on the usage of the Intel software development and diagnostic tools. The pre-requisite for this class is the one-day seminar CDT 101.

9 am to 4 pm: Hands-on sessions
-Offload and Native: "Hello World" to complex; using MPI.
-Performance Analysis: VTune.
-Case Study: all aspects of tuning in the N-body calculation.
-Optimization I: strip-mining for vectorization, parallel reduction.
-Optimization II: loop tiling, thread affinity.

Intel Xeon Phi coprocessors, featuring the Intel Many Integrated Core (MIC) architecture, are novel many-core computing accelerators for highly parallel applications, capable of delivering greater performance per system and per watt than general-purpose CPUs. Unlike GPGPUs, they support traditional HPC programming frameworks, including OpenMP and MPI, and require the same software optimization methods as multi-core CPUs.

Schedule:

Time    Topic
8:30 AM - 9:00 AM                Registration
9:00 AM - 9:30 AM                Remote Access Configuration, Lab Orientation
9:30 AM - 10:30 AM              Programming with Explicit Offload
10:30 AM - 11:00 AM            Native Programming
11:00 AM - 12:00 PM             Performance Analysis
12:00 PM - 1:00 PM               Lunch Break
1:00 PM - 2:00 PM                 Comprehensive optimization: N-body calculation
2:00 PM - 3:00 PM                 Partnering vectors and cores: histogram example
3:00 PM - 4:00 PM                 Boosting memory and cache traffic: transposition example

Please distribute to faculty, staff and students that might be interested.

Thanks,

Feng Chen, Ph.D.
IT Consultant
329, Frey Computing Services Center,
Louisiana State University,
Baton Rouge, LA 70803
Voice: (225) 578-2924
eMail: fchen14 at lsu.edu<mailto:fchen14 at lsu.edu>


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