[LA-SiGMA-TESC] FW: XSEDE Training: Optimize Your Code for the Intel XEON Phi 2/21

[Wei P Feinstein]

Hi all,

The originally scheduled training on Xeon Phi has been cancelled due to the winter storm.  Now it is rescheduled and open for registration.  Take advantage of it if you are interested.  

Best,
Wei
________________________________________
From: XSEDE User News <news at xsede.org>
Sent: Thursday, January 30, 2014 5:44 PM
Subject: XSEDE Training: Optimize Your Code for the Intel XEON Phi 2/21

A new message has been posted to XSEDE User News.

Categories: Training, General User News, Stampede (TACC)

Posted on 30 Jan, 2014 23:34 UTC by Bob Garza

**XSEDE Training: Optimize Your Code for the Intel XEON Phi**

February 21, 2014 (Friday)
9 a.m. to 5 p.m. (CT)
ROC 1.900

Texas Advanced Computing Center
J.J. Pickle Research Campus
10100 Burnet Rd.
Austin, TX 78758

**You may attend this class in person or via webcast.**

This class is intended for intermediate to advanced users of Stampede.  Attendees are expected to be able to program using MPI and OpenMP.  The Innovative Technology component of the XSEDE Stampede supercomputer at TACC provides access to 8 PetaFlops of computing power in the form of the Intel Xeon Phi Coprocessor, also known as MIC. While the MIC is x86 based, hosts its own Linux OS, and is capable of running most user codes with little porting effort, the MIC architecture has significant features that are different from that of present x86 CPUs, and optimal performance requires an understanding of the possible execution models and basic details of the architecture. This workshop is designed to introduce Stampede users to the MIC architecture in a practical manner. Multiple lectures and hands-on exercises will be used to get the user acquainted with the MIC platform and explore the different execution modes as well as parallelization and optimization through example testing and reports.  Users are also welcome to bring their own codes to compile for MIC.

The workshop will be divided in four sections: Introduction to the MIC architecture; native execution and optimization; offload execution; and symmetric execution. In each section the users will spend half the time doing guided hands-on exercises.

The exercises will be available for remote users.  However, we will not be able to assist remote users with problems during the exercises.

**Registration:** "https://www.xsede.org/web/xup/course-calendar":https://www.xsede.org/web/xup/course-calendar

Please submit any questions you may have via the Consulting section of the XSEDE User Portal.
"https://portal.xsede.org/help-desk":https://portal.xsede.org/help-desk

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