[LA-SiGMA-gpu] TACC Training: Optimize Your Code for the Intel XEON Phi

[Wei P Feinstein]

Hi All,

The registration of TACC training: Optimize Your Code for the Intel XEON Phi has started.  We are going to webcast this training in 1008B DMC on 10/4.  In order to get hands on experience, you need to register at 
http://www.tacc.utexas.edu/user-services/training/optimize-your-code-for-the-intel-xeon-phi-10-4.

Let me know if there is any question.

Wei

Wei Feinstein, Ph.D.
Computational Biology
Louisiana State University
E-mail: wfeinstein at lsu.edu
Lab: http://brylinski.cct.lsu.edu/
Office: 401 Choppin Hall, 2060 DMC
Tel: 251-599-3814

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_______________________________________________
>     TACC Training: Optimize Your Code for the Intel XEON Phi 10/4
>
>     From: Bob Garza
>
>     TACC Training: Optimize Your Code for the Intel XEON Phi
>
>     October 4, 2013 (Friday)
>     8:30 a.m. to 5 p.m. (CT)
>     ROC 1.900
>
>     Texas Advanced Computing Center
>     J.J. Pickle Research Campus
>     10100 Burnet Rd.
>     Austin, TX 78758
>
>     You may attend this class in person or via webcast.
>
>     This class is intended for intermediate to advanced users of
>     Stampede. Attendees are expected to be able to program using MPI
>     and OpenMP.
>
>     The Innovative Technology component of the recently deployed XSEDE
>     Stampede supercomputer at TACC provides access to 8 PetaFlops of
>     computing power in the form of the new Intel Xeon Phi Coprocessor,
>     also known as MIC. While the MIC is x86 based, hosts its own Linux
>     OS, and is capable of running most user codes with little porting
>     effort, the MIC architecture has significant features that are
>     different from that of present x86 CPUs, and optimal performance
>     requires an understanding of the possible execution models and
>     basic details of the architecture. This workshop is designed to
>     introduce Stampede users to the MIC architecture in a practical
>     manner. Multiple lectures and hands-on exercises will be used to
>     get the user acquainted with the MIC platform and explore the
>     different execution modes as well as parallelization and
>     optimization through example testing and reports. Users are also
>     welcome to bring their own codes to compile for MIC.
>
>     The workshop will be divided in four sections: Introduction to the
>     MIC architecture; native execution and optimization; offload
>     execution; and symmetric execution. In each section the users will
>     spend half the time doing guided hands-on exercises.
>
>     The exercises will be available for remote users. However, we will
>     not be able to assist remote users with problems during the
>     exercises.
>
>     Registration
>
>     Please submit any questions you may have via the TACC Consulting
>     System: http://portal.tacc.utexas.edu/consulting/
>